Timing
Metastability
An unstable state where a flip-flop's output is undefined, occurring when setup or hold time is violated.
Detailed Explanation
When data changes too close to the clock edge, the flip-flop may enter metastability—the output voltage lingers between valid logic levels before eventually resolving to 0 or 1. Resolution time is probabilistic and theoretically unbounded.
Metastability is unavoidable when asynchronous signals enter synchronous domains. Synchronizers (two or more flip-flops in series) reduce metastability probability to acceptable levels—each additional flip-flop provides another clock period for resolution.