Timing
Synchronizer
A circuit that safely transfers signals between different clock domains, mitigating metastability.
Detailed Explanation
A two-flop synchronizer chains two flip-flops on the destination clock. If the first flop goes metastable (input sampled near its transition), it has one clock period to resolve before the second flop samples it. The probability of both flops going metastable is extremely low.
Single-bit synchronizers suffice for individual signals. Multi-bit signals require either gray coding (where only one bit changes), handshake protocols, or asynchronous FIFOs to prevent data corruption.