Timing
Hold Time
The minimum time a data signal must remain stable after the clock edge for reliable flip-flop capture.
Detailed Explanation
Hold time ensures the flip-flop has completed sampling before data changes. Violating hold time (data changing too soon after clock edge) can cause metastability or incorrect capture. Hold violations are independent of clock frequency.
Hold time is measured from the clock edge. Faster clock-to-Q data arrival from the previous register can cause hold violations. Adding delay buffers fixes hold violations without affecting cycle time.