Sequential Design
Moore Machine
A finite state machine where outputs depend only on the current state, not directly on inputs.
Detailed Explanation
Moore machine outputs are associated with states, not transitions. Output changes occur one clock after the input change that caused the state transition. This creates a registered output, simplifying timing at interfaces.
Moore machines typically need more states than equivalent Mealy machines because output differences require different states. However, the cleaner output timing often justifies the extra states.
Code Example
systemverilog
// Moore FSM - output depends only on state
typedef enum logic [1:0] {IDLE, RUN, DONE} state_t;
state_t state_q;
always_ff @(posedge clk or posedge reset) begin
if (reset)
state_q <= IDLE;
else case (state_q)
IDLE: state_q <= start ? RUN : IDLE;
RUN: state_q <= finish ? DONE : RUN;
DONE: state_q <= IDLE;
endcase
end
// Output is purely a function of state
assign busy = (state_q == RUN);
assign complete = (state_q == DONE);