Digital Logic
Overflow
The condition when an arithmetic result exceeds the representable range, causing incorrect results.
Detailed Explanation
Unsigned overflow occurs when addition produces a carry out of the MSB. Signed overflow occurs when the sign of the result is wrong—adding two positives yields negative, or adding two negatives yields positive.
Hardware detects overflow by comparing the carry into and out of the MSB (for signed). Overflow flags in ALUs inform software of these conditions. Saturating arithmetic clamps results to min/max instead of wrapping.