Architecture
Ordering
Rules governing the sequence in which memory operations become visible to different observers in a system.
Detailed Explanation
Memory ordering defines when writes by one processor become visible to others. Strong ordering (sequential consistency) makes all operations appear in program order—simple but limits optimization. Weak ordering allows reordering for performance, requiring explicit barriers.
Hardware implements ordering through store buffers, cache coherence, and interconnect ordering rules. Memory barriers (fences) enforce ordering when needed. Incorrect ordering causes subtle concurrency bugs.