Architecture
Performance Counter
Hardware registers that count events (instructions, cache misses, cycles) for performance analysis and profiling.
Detailed Explanation
Performance counters track microarchitectural events during execution. Software reads counters to identify bottlenecks—high cache miss rates suggest memory issues; low IPC might indicate stalls. Counters typically have programmable event selectors.
Counter overflow can trigger interrupts for sampling-based profiling. Hardware timestamps enable precise latency measurement. Multiple counters allow correlation of different events.