Timing
Propagation Delay
The time for a signal change at a gate input to cause the corresponding change at its output.
Detailed Explanation
Every logic element has non-zero delay—inputs change, then outputs respond after tpd. Delay depends on gate type, load capacitance, input transition speed, and operating conditions (voltage, temperature). Rise and fall delays may differ.
Total path delay is the sum of gate delays plus wire delays along a path. The critical path (longest delay) limits maximum clock frequency. Timing optimization targets critical paths.