Sequential Design
Sequence Detector
An FSM that identifies a specific pattern in a serial input stream, asserting an output when the pattern occurs.
Detailed Explanation
Sequence detectors track progress through a target pattern using states. Each state represents how much of the pattern has been matched. Correct design handles overlapping patterns—where the end of one match is the beginning of another.
Implementation approaches include explicit FSMs and shift registers with comparators. Shift registers are simpler for fixed patterns; FSMs handle pattern variations and wildcards.
Code Example
systemverilog
// Sequence detector using shift register (pattern: 1011)
module seq_det_1011 (
input logic clk, reset, x,
output logic det
);
logic [3:0] shift_reg;
always_ff @(posedge clk or posedge reset) begin
if (reset)
shift_reg <= 4'b0;
else
shift_reg <= {shift_reg[2:0], x};
end
assign det = (shift_reg == 4'b1011);
endmodule