Sequential Design
Synchronous Reset
A reset signal that takes effect only on the active clock edge, not immediately.
Detailed Explanation
Synchronous reset updates flip-flops to their reset state on the next clock edge after reset assertion. This means reset is another input to next-state logic. Reset timing is predictable but requires clocks to be running for reset to take effect.
Synchronous reset simplifies timing analysis and can reduce logic complexity by using the reset path for optimization. However, clocks must be stable during reset, which isn't always guaranteed at power-on.
Code Example
systemverilog
// Synchronous reset flip-flop
always_ff @(posedge clk) begin
if (sync_reset)
q <= '0; // Reset on clock edge
else
q <= d;
end