Sequential Design
Asynchronous Reset
A reset signal that immediately forces registers to their initial state regardless of clock state.
Detailed Explanation
When an asynchronous reset is asserted, flip-flops transition to their reset state without waiting for a clock edge. This provides immediate, deterministic initialization. The reset is typically in the sensitivity list of sequential blocks.
The challenge comes with reset de-assertion. If reset releases close to a clock edge, metastability can occur. The solution is reset synchronization: assert asynchronously (immediate effect) but de-assert synchronously (coordinated with clock).
Code Example
systemverilog
// Asynchronous reset flip-flop
always_ff @(posedge clk or posedge reset) begin
if (reset)
q <= '0; // Immediate reset
else
q <= d;
end
// Reset synchronizer for safe de-assertion
always_ff @(posedge clk or posedge async_reset) begin
if (async_reset)
{sync_reset, reset_pipe} <= '1;
else
{sync_reset, reset_pipe} <= {reset_pipe, 1'b0};
end