HDL Concepts
Wire
A signal type in Verilog/SystemVerilog representing a physical connection driven by continuous assignments or module outputs.
Detailed Explanation
Wires model physical connections—they don't store values but carry whatever their drivers produce. Multiple drivers require resolution rules (usually creating 'x' for conflicting values). Wires are used for combinational signals and interconnections.
Logic type in SystemVerilog unifies wire and reg, allowing assignment from both continuous and procedural contexts. Modern code typically uses logic unless specific wire behavior is needed.