Branch Control
The logic that decides whether a branch instruction is taken and computes the resulting program counter.
Detailed Explanation
Branch control compares two register values according to the branch's funct3 (BEQ, BNE, BLT, BGE, BLTU, BGEU) and produces a single `branch_taken` signal. If taken, the next PC becomes `PC + imm_B`, where `imm_B` is the sign-extended branch offset; if not, fetch continues sequentially. The branch target adder usually lives alongside the main ALU but is kept separate so that branches can resolve without contending for the arithmetic unit.
A subtle but important point: in RISC-V, branches compute their target from `PC` — not from `rs1`. That is what distinguishes them from indirect jumps (JALR), which *do* use `rs1` as a base. Mixing these up is one of the most common RTL bugs when building a first-time core, because the rest of the pipeline already drives `rs1` into the ALU and it's tempting to reuse that path.
Industry Context
Even tiny cores track branch mispredictions in a performance counter; on deeper pipelines every branch bubble costs several cycles, making the branch unit a prime target for prediction and early-resolve optimizations.