Instruction Decode
The pipeline stage that interprets an instruction's bit fields to extract the opcode, register specifiers, and immediate values.
Detailed Explanation
Decode turns raw instruction bits into control signals the rest of the pipeline can use. It splits the instruction word into fields — opcode, funct3, funct7, rs1, rs2, rd in RISC-V — and hands them to the control unit and register file. It also builds the immediate operand by sign-extending the scattered immediate bits into a full 32-bit value, following the format-specific encoding (I/S/B/U/J).
The complexity of decode depends on the ISA. Fixed-length RISC formats like RISC-V keep decode purely combinational and cheap; CISC or variable-length encodings need multi-cycle decoders, pre-decode caches, or micro-op translation. Decode is also where illegal-instruction exceptions are first detected.
Industry Context
On wide superscalar cores, decoders are often a throughput bottleneck — vendors replicate them per issue lane and invest heavily in the micro-op cache to avoid re-decoding hot loops.
Code Example
// RISC-V R-type / I-type field extraction
module decode (
input logic [31:0] instr,
output logic [6:0] opcode,
output logic [4:0] rs1, rs2, rd,
output logic [2:0] funct3,
output logic [6:0] funct7,
output logic [31:0] imm_i
);
assign opcode = instr[6:0];
assign rd = instr[11:7];
assign funct3 = instr[14:12];
assign rs1 = instr[19:15];
assign rs2 = instr[24:20];
assign funct7 = instr[31:25];
assign imm_i = {{20{instr[31]}}, instr[31:20]};
endmodule