Sequential Design
Edge Detection
A circuit that detects transitions (rising edge, falling edge, or both) on an input signal.
Detailed Explanation
Edge detectors produce a pulse when the input transitions. A rising edge detector compares the current input with its delayed (registered) version—a pulse occurs when current is high but delayed is low. Falling edge detectors invert the comparison.
Edge detection converts level signals to pulse signals, triggering actions once per transition rather than continuously while active. This is essential for button debouncing, protocol decoding, and event generation.
Code Example
systemverilog
// Rising and falling edge detection
module edge_detect (
input logic clk, reset, sig_i,
output logic rise_o, fall_o
);
logic sig_q;
always_ff @(posedge clk or posedge reset) begin
if (reset)
sig_q <= 1'b0;
else
sig_q <= sig_i;
end
assign rise_o = sig_i & ~sig_q; // Current high, previous low
assign fall_o = ~sig_i & sig_q; // Current low, previous high
endmodule