HDL Concepts
Parameterizable Design
Design technique using parameters to create configurable, reusable modules with variable widths, depths, or features.
Detailed Explanation
Parameters let a single module definition serve multiple use cases. A parameterized FIFO can be instantiated as 8-deep or 64-deep by changing a parameter. Parameters propagate through hierarchy, enabling systematic configuration.
SystemVerilog parameters can be types, integers, or arrays. Generate blocks create structure based on parameters. Parameterization is fundamental to IP reuse—one UART design serves projects with different clock rates or buffer sizes.
Code Example
systemverilog
module fifo #(
parameter int WIDTH = 8,
parameter int DEPTH = 16,
parameter int ALMOST_FULL_THRESH = DEPTH - 2
) (
input logic clk, reset,
input logic [WIDTH-1:0] data_in,
// ... other ports
);
logic [WIDTH-1:0] mem [0:DEPTH-1];
logic [$clog2(DEPTH)-1:0] wr_ptr;
// ...
endmodule