Parallel-to-Serial Converter
A circuit that accepts multiple bits in parallel and transmits them one bit at a time over successive clock cycles.
Detailed Explanation
A parallel-to-serial converter takes a wide data word and turns it into a serial stream. This is useful whenever internal logic operates on words but an external interface, storage format, or downstream block expects one bit per cycle. The circuit typically consists of a loadable register plus shift logic that emits one bit on each clock edge after the word is captured.
The main design questions are bit ordering, framing, and throughput. Some designs send the most significant bit first; others send the least significant bit first. Some emit a separate valid signal or start bit, while others rely on fixed timing. If a new word arrives before the current one finishes shifting, the converter also needs buffering or back-pressure logic.
Code Example
module p2s #(
parameter WIDTH = 8
) (
input logic clk, rst_n,
input logic load,
input logic [WIDTH-1:0] data_i,
output logic bit_o
);
logic [WIDTH-1:0] shreg_q;
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n)
shreg_q <= '0;
else if (load)
shreg_q <= data_i;
else
shreg_q <= {shreg_q[WIDTH-2:0], 1'b0};
end
assign bit_o = shreg_q[WIDTH-1];
endmodule