Verification
Zero-Delay Simulation
Simulation where combinational logic is modeled with zero propagation delay, showing functional behavior without timing effects.
Detailed Explanation
Zero-delay (functional) simulation assumes all logic is instantaneous. Outputs change immediately when inputs change within the same simulation time. This is appropriate for RTL verification where timing isn't modeled.
Gate-level simulation can include cell delays (SDF annotation) for timing verification. Zero-delay gate-level simulation checks functional correctness after synthesis. Unit-delay simulation uses nominal delays for all elements.