APB Interface
The SystemVerilog interface construct that bundles the APB signal set so masters, slaves, and testbench components can connect through a single handle.
Detailed Explanation
An APB *interface* in the SystemVerilog sense is the clean way to wire together every APB participant. It groups `pclk`, `presetn`, `paddr`, `pwrite`, `psel`, `penable`, `pwdata`, `prdata`, `pready`, and `pslverr` into one named bundle, then uses `modport` to hand out the master-view and slave-view of that bundle so each side only sees the signals it's allowed to drive. For verification, a third modport — typically `monitor` — gives read-only access to every signal.
Using an interface instead of a long port list is what makes APB testbenches scalable. Drivers, monitors, and the DUT all take a single `virtual apb_if` handle, clocking blocks on the interface prevent race conditions on every sampled signal, and swapping a DUT for a different slave becomes a one-line change. The same pattern applies to AXI, AHB, and any other protocol with a wide signal set.
Code Example
interface apb_if (input logic pclk, input logic presetn);
logic [31:0] paddr, pwdata, prdata;
logic psel, penable, pwrite, pready, pslverr;
clocking master_cb @(posedge pclk);
default input #1step output #1;
output paddr, pwdata, psel, penable, pwrite;
input prdata, pready, pslverr;
endclocking
modport master (clocking master_cb, input presetn);
modport slave (input paddr, pwdata, psel, penable, pwrite, pclk, presetn,
output prdata, pready, pslverr);
modport monitor (input paddr, pwdata, prdata, psel, penable, pwrite,
pready, pslverr, pclk, presetn);
endinterface