Verification

Generator

A testbench component that creates transaction objects and feeds them to downstream components such as drivers or sequencers.

Detailed Explanation

A generator is the source of stimulus intent in a transaction-level testbench. It decides what kind of traffic to create, how many operations to send, and which corner cases to emphasize. In a simple directed environment, the generator may emit a short predetermined list of reads and writes. In a constrained-random environment, it produces many randomized transactions while still respecting protocol and scenario constraints.

The generator typically does not drive pins directly. Instead, it hands transactions to a driver through a mailbox, queue, or sequence interface. This separation keeps protocol timing in the driver and leaves stimulus policy in one place, which makes the environment easier to extend and debug.

Code Example

systemverilog
class apb_generator;
  mailbox #(apb_txn) out_mbx = new();

  task run(int n = 10);
    repeat (n) begin
      apb_txn t = new();
      assert(t.randomize());
      out_mbx.put(t);
    end
  endtask
endclass