Instruction Memory
The memory region that stores a program's instructions, addressed by the program counter during fetch.
Detailed Explanation
Instruction memory holds the compiled program and is read — usually not written — by the fetch stage. In a simple single-cycle or pipelined core it is modeled as a synchronous-read SRAM or a simple ROM, addressed by the PC and returning one instruction per cycle. A Harvard-style split memory keeps it physically separate from data memory so that instruction fetch and data access can happen in parallel every cycle.
In a full system, this abstraction is replaced by an instruction cache sitting in front of a unified backing store. The cache hides main-memory latency from the pipeline and, on ASICs, is often the largest RAM on the die. Bootloaders, page tables, and self-modifying code complicate the read-only assumption — which is why real cores include cache-flush instructions and coherence logic.