Scoreboard
A testbench component that keeps a parallel reference model and checks DUT outputs against expected values on every transaction.
Detailed Explanation
The scoreboard is the correctness arbiter of a testbench. Whenever the monitor sees a transaction on the DUT interface, it forwards a copy to the scoreboard; the scoreboard either holds it in a queue or compares it against a prediction coming from a reference model. A mismatch is reported immediately, usually with enough context (transaction ID, cycle, field deltas) to jump straight to the failing trace.
Scoreboards come in two flavors: *in-order*, where outputs are expected in the same order they were driven in, and *out-of-order*, where responses can interleave and the scoreboard has to match them up by tag or address. APB, being a strictly ordered protocol, is the easy case — every response lines up with the driver's generated transaction queue. AXI or PCIe scoreboards are much harder because they must track outstanding tags and latencies.
Industry Context
In UVM, the scoreboard is a `uvm_component` that subscribes to analysis ports from monitors on both sides of the DUT; in Verilog-only testbenches it's often just a mailbox plus a compare task.
Code Example
class apb_scoreboard;
mailbox #(apb_txn) expected_mbx = new();
task check(apb_txn observed);
apb_txn exp;
expected_mbx.get(exp);
if (observed.addr !== exp.addr || observed.data !== exp.data)
$error("MISMATCH addr=%h exp_data=%h got=%h",
observed.addr, exp.data, observed.data);
endtask
endclass